Crenel Logic: Hardware-Enforced AI Containment (MIL-SPEC Beta Build)

The Vision

At Crenel Logic, Inc., our philosophy is built into our name: like a crenel in a fortress, AI should offer the ultimate window for human agency while providing an impenetrable physical shield for our protection. We are building a deterministic, hardware-in-the-loop containment system for agentic AI and autonomous robotics.

The Problem

Current AI alignment relies on software-based guardrails that are fundamentally vulnerable to adversarial attacks, corruption, and non-deterministic errors. When a system can rewrite its own code or manipulate its software environment, a digital "stop button" is insufficient. We need a safety architecture governed by immutable physical laws (specifically gravity, inertia, and thermodynamics).

The Solution

Our architecture bridges a formal verification logic layer with a galvanically isolated electromagnetic containment loop.

• The Logic Layer: We utilize a Retrieval-Augmented Constitutional Constraint Engine and an SMT solver (e.g., Z3) as a strict logic gate.

• The Physical Layer: If the SMT solver returns an 'UNSAT' (Unsatisfiable) result due to a safety violation, it generates a high-priority hardware interrupt. This cuts voltage to a "Normally Open" solenoid, allowing a gravity-biased interlock to physically drop and sever motive power. The system defaults to containment upon any unsafe, stale, or absent verification state.

• The Containment Enclosure: To neutralize the risk of wireless data exfiltration or secondary communication bridging during an interrupt event, the core compute hardware is fully secured within a Faraday cage.Traction & Recent Progress

• The Team: Kay Astle (Founder/Architect) leads the formal verification design, logical constraint engineering, and physical hardware prototyping. Scott Novak (Co-Founder) manages AI-assisted software synthesis and system orchestration, leveraging generative models to rapidly translate core logic into a functional software engine.

• IP Secured: We have filed three comprehensive provisional patents covering our VSPE (Validation, Stability, Positivity, Empowerment) middleware, inertial locking mechanisms, and the hardware-in-the-loop translation bridge.

• Physical Prototype: We successfully completed our hardware sprint, resulting in a fully functional physical breadboard of the gravity lock.

• Public Demonstration: We recently presented our kinetic severance prototype live at the Manifest conference.How Funds Will Be Used

We are raising $40,000 to execute Phase 3 of our Master Execution Plan: Beta Manufacturing, Third-Party Audits, and International IP Fortification.

• Beta Manufacturing & Audits ($25,000): We will manufacture a targeted batch of 5 to 7 ruggedized Beta units, potting the logic boards in tamper-evident frangible glass-sphere epoxy. These units will be split directly between top alignment research labs (such as METR and Apollo) for rigorous, concurrent red-team testing of our electromechanical inertial trip mechanism, with a reference pair kept in-house for real-time replication of any discovered vulnerabilities.
• International IP Defense Buffer ($15,000): This capital will protect the architecture globally, providing the necessary funding to transition our active provisional patents into one international utility patent (PCT) while our hardware undergoes evaluation.